1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a memory device that can be tested without using data and a dataless test method.
2. Description of the Related Art
As memory devices are highly integrated and production scale of the memory devices continually increases, demand for testers which can carry out parallel tests for large-capacity memory devices also increases. However, the number of test dies of the tester is limited because the number of test signals corresponding to the number of signals of a memory device is limited.
Furthermore, as the operating frequencies of memory devices increase, a high-speed tester is required. In the case of 512M DDR2 DRAM, for example, the total number of signals of a tester used to test a single DDR2 DRAM is forty-eight, which includes twenty-six command/address signals, two clock signals and twenty data signals. To test the DDR2 DRAM, the data signals have to be applied to the DDR2 DRAM at a high operating frequency while the command/address signals can be applied to the DDR2 DRAM at a frequency corresponding to half the high operating frequency of the DDR2 DRAM. Accordingly, when the DDR2 DRAM is tested using a high-speed tester, the number of test dies capable of performing a parallel test is determined (e.g., limited) by the number of data signals.
Therefore, a need exists for a test method and a test device which does not restrict the number of parallel test dies. A need also exists for a test method and a test device which does not provide data signals that restrict the number of parallel test dies. Finally, a need exists for a test method and a test device where a tested DRAM provides fewer data signals to increase the number of parallel test dies required to test the DRAM.